Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering

Abstract

A custom FPGA emulation platform for the verification of a slowly adapted, background calibration technique for successive-approximation-register (SAR) analog-to-digital converter (ADC) is demonstrated in an Altera DE4 board. The internal redundancy of a sub-binary SAR is exploited for the identification of ten leading bit weights in a 14.5-bit SAR ADC using pseudorandom bit sequence (PRBS) injection with background correlation. Experimental results reveal that the FPGA emulation achieves a 3000× speedup for the same simulation executed on a general-purpose microprocessor.