Fast error-correcting circuits for fault-tolerant memory

Abstract

This work explores the design and analysis of an error-correcting circuit as applied to high density and low latency memories, especially NOR Flash and DRAM. In very high density semiconductor memory products, exhaustive testing and repair procedures are essential to insure the proper operation of every memory location under worst possible conditions and can account for a significant portion of the total production cost. The implementation of error-correcting circuits in conjunction with other currently-used methods for designing more fault-tolerant high density memory could allow for more simplified testing procedures after memory fabrication and significantly reduce the overall cost. Also, error-correcting circuits could increase the reliability of the memory and extend its lifetime. This paper illustrates one possible implementation of error-correcting circuits, in the form of a Hamming decoder. Clocking was accomplished with asynchronous pulse generators to ensure fast cycle times and minimal decoding delay. These circuits were designed to show that error correction can be achieved with minimal additional circuitry, system complexity, power consumption and latency.