Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures

Abstract

Electromigration (EM) has become one of the most significant challenges considering longterm reliability in integrated circuit design. The problem is caused by the large current density in circuit interconnections. However, in most cases, we are interested in the EM stress at specific points of the interconnect, such as vias, junctions and boundaries. As a result, Model Order Reduction (MOR) techniques can provide attractive methodologies to reduce the complexity of the original systems. System-theoretic techniques like Balanced Truncation (BT) offer very reliable bounds for the approximation error, compared to moment-matching methods. In this paper, we apply a computationally efficient Low-Rank BT procedure based on the extended Krylov subspace method, that can handle large-scale models and significantly accelerate the EM stress analysis for any general interconnect or power grid structure. For the experimental evaluation, we first consider a general structure interconnect tree to demonstrate the generalizability of the proposed method and then we employ our method on the industrial IBM power grid benchmarks where the its scalability is shown. For the latter, we demonstrate that our method can achieve a speedup up to 238× over a standard transient analysis method and a speedup up to 15× over COMSOL, while exhibiting negligible error.