Abstract
A methodology for fast and accurate estimation of the number and positions of buffers during 3D IC floorplanning is developed. Our algorithm computes candidate buffer positions simultaneously with assignment of 3D nets to TSVs. Through accurate delay characterization of buffered 3D nets, the minimum distance between consecutive buffers is estimated. Additionally, an analytical approach is used to find the optimal position of buffers in front of TSVs. This prevents additional buffers' insertion around TSVs, incurring lesser delay and power in 3D nets. Experimental results with expanded GSRC benchmarks show 5.6% more reduction in number of buffers, 5.7% reduction in interconnect delay and 4% reduction in dynamic power, compared to a previous published work. The potential impact of nanoscale TSVs on buffer estimation at sub-45 nm technologies is analyzed.
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