Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells

Abstract

Transistor network optimization is an effective way of improving the VLSI circuit design. Recent papers demonstrate the graph-based or library-based methodologies of the supergate (SG) design. This design approach is the direct design of the functions at the transistor level that can provide circuits with fewer transistors when compared with the conventional methods. In addition to the transistor count, the symmetry structure of the circuit, the number of transistors on the critical path, and multi-outputs and multi-functional cells are considered in this paper, as the three crucial parameters for the efficient SG cell design. Thus, the cell design methodology (CDM) logic style is used as a new approach for the SG design with some changes in the design flow for improving circuit characteristics. The proposed CDM-SG design methodology can produce a single output, complementary output, and multi-functional output SG cells. The comparison of the proposed CDM-SG cells with conventional SG cells shows a significant improvement on the layout area, power and energy consumption, and speed. The proposed CDM-SG cells with spiral structure are multi-output and multi-functional cells, which can significantly improve the circuit characteristics by improving the number of output functions over the cell area.