Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures

Abstract

Owning to rapid growth in standard-cell-based synthesized designs; the efficiency of standard cells has increasingly become important. In this line, the Cell Design Methodology (CDM) has systematically meditated to present some new efficient designs such as three 2-input XORs and full adder in hybrid CMOS logic style which are the most significant and crucial building block in arithmetic units as well as multiplier structures. For the best cell design, energy considered as optimization parameter for the transistor sizing and the trade-off between the PDP and driveability of the cells has been investigated. The goal is finding energy-efficient cells for an expected range of the output loads which is essential in multi-stage structures. In this way, average PDP has been calculated at each value of the load capacitance and finally load capacitance corresponding to minimum average PDP is selected for cell sizing. Different ranges of the load capacitance are selected for the cells with different drive capability. Therefore designed cells shows the minimum PDP variation with variation in load capacitance as with multistage logic synthesis. While the efficiency of the proposed designs has confirmed in many test benches, this work evaluates the performance of the new circuits in the form of standard cells besides the standard cell library of TSMC 130nm technology in real and more practical structures like 8-bit, 16-bit, 32-bit, and 64-bit multipliers in the layout level. To size, characterize, simulate of the cells and compile the structures, HSPICE, Encounter Library Characterizer (ELC), SPECTRE, and Design Compiler (DC) are employed. The result of the analysis shows that the contribution percentage of the new cells are increasing in larger structures from 15.2% to 19.8% which leads to 3%-49.3% improvement in power-delay product compared with using the regular standard cell library solely.