Abstract

Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accuracy problem or modeling efforts that are caused by the absence of modeling framework or requiring in-depth knowledge of specific behaviors of target NoCs. To support cycle-accurate and formal high-level modeling framework, we propose a cellular automata (CA) modeling framework for RTL NoC. The CA abstracts detailed RTL NoC dynamics into the proposed high-level state transitions, which support flit transmission among CA components through dynamically changing flit paths based on the target RTL routing and arbitration algorithms. To prevent the meaningless execution of stable CA, the CA are designed to be triggered by state-change events. The proposed simulation engine asynchronously invokes CA to update their states and perform actions of flit transmissions or flit-path changes based on the state-decision result. To reduce the modeling difficulty, we provide a test environment that generates the state-transition rules for CA after monitoring the relationships between high-level states and leading actions under randomly injected packets during target RTL NoC simulations. Experiments demonstrate cycle-level functional homogeneity between RTL and the abstracted CA NoC models and significant simulation speedup.

Highlights

  • Advances in nanoscale semiconductor technology enable the integration of a large number of intellectual property (IP) blocks on a single chip to meet application-specific highperformance requirements for system-on-chip (SoC)

  • We proposed a high-level NoC modeling framework and its simulation engine based on event-driven cellular automata (CA) execution to abstract the detailed register-transfer level (RTL) operations and invoke active cells, rather than executing stable CA

  • The proposed CA represent the operations of the target RTL NoC as state transitions of three types of cells: buffer cell (BC), coupling cell (CC), and path-viability cell (PV)

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Summary

INTRODUCTION

Advances in nanoscale semiconductor technology enable the integration of a large number of intellectual property (IP) blocks on a single chip to meet application-specific highperformance requirements for system-on-chip (SoC). When the NoC implementation or IP combinations (which can produce different packet-generation patterns) are changed, the corresponding queueing model should be customized through reformulation or parameter resetting based on newly collected plenty of simulation data The modeling framework is formally designed based on the cellular automata (CA) concept [13]–[15], which describes the target NoC using a finite number of CA components with a regular connectivity pattern and each component updates its high-level states using its own and its neighbors’ states at each. The proposed formal modeling framework enables the derivation of action-state decision rules by probing changes of those RTL signals that relate to high-level states.

CELLULAR AUTOMATON MODELING OF RTL NOC
IMPLEMENTATIONS FOR THE δ AND η FUNCTIONS USING DECISION RULES
TEST ENVIRONMENT OF RTL NOC DESIGNS
DECISION-RULE DERIVATION IN TEST LIBRARY
EXPERIMENTATION
CONCLUSION
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