Simulation analysis and performance evaluation of four innovative routers for network on chip

Abstract

Network on Chip (NOC) a new design emerging offers a promising architectural choice for future systems on chips. NOC architectures offer a packet switched communication among functional cores on the chip. NOC architectures also apply concepts from computer. In our work we analysed the series of simulation results of four innovative routers. All the results are useful for design of an appropriate switch for the NOC. This work reports experimental results based on the simulation of four innovative routers using verilog in modelsim enviornment. Performance analysis is also done by comparing their simulation results. Performance analysis is usually done by simulation at the Transaction Level — TL or at the Register Transfer Level — RTL. TL provides smaller simulation time, while RTL provides more accuracy in results, which is very necessary during the design phase of a NoC. However, the performance characterization of a large NoCs by means of RTL simulation is time costly and requires several hours of computing. The performance evaluation of a NoC can be also speeded up by doing it directly on hardware as FPGA instead of using simulation models.