Abstract
The impact of process variation has been more prominent in nano-technology, and it poses great challenge to timing analysis for digital VLSI. Traditionally, this problem is solved by using statistical static timing analysis (SSTA). However, static timing analysis may lead to an overly pessimistic estimation, as many critical paths are not true paths. In this paper, we present a fast SSTA method, in which critical path traversal is combined with false path analysis so that true critical paths can be quickly identified. Experimental results show that a significant portion of the longest paths are actually false, which implies SSTA without false path analysis usually overestimate critical path delays.
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