Statistical static timing analysis: A survey

Abstract

As the device and interconnect physical dimensions decrease steadily in modern nanometer silicon technologies, the ability to control the process and environmental variations is becoming more and more difficult. As a consequence, variability is a dominant factor in the design of complex system-on-chip (SoC) circuits. A solution to the problem of accurately evaluating the design performance with variability is statistical static timing analysis (SSTA). Starting from the probability distributions of the process parameters, SSTA allows to accurately estimating the probability distribution of the circuit performance in a single timing analysis run. An excellent survey on SSTA was recently published [D. Blaauw, K. Chopra, A. Srivastava, L. Scheffer, Statistical timing analysis: from basic principles to state of the art, IEEE Trans. Computer-Aided Design 27 (2008) 589–607], where the authors presented a general overview of the subject and provided a comprehensive list of references. The purpose of this survey is complementary with respect to Blaauw et al. (2008), and presents the reader a detailed description of the main sources of process variation, as well as a more in-depth review and analysis of the most important algorithms and techniques proposed in the literature that have been applied for an accurate and efficient statistical timing analysis.