Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Henning Gundersen,Yngvar Berg

doi:10.1109/ismvl.2007.23

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

Henning Gundersen, Yngvar Berg

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https://doi.org/10.1109/ismvl.2007.23

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Publication Date: May 1, 2007

Citations: 19

Affiliation: University of Oslo

#Balanced Ternary #Ternary Counters + Show 8 more

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Abstract

This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.

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