Synthesis of Balanced Ternary Reversible Logic Circuit

Abstract

Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2. The paper addresses the synthesis of balanced ternary reversible logic circuit and design of reversible half-adder and full-adder circuit by using balanced ternary reversible logic gates. We also introduce balanced ternary multiplier gate that is used to design of single trit and multi-trit multiplier circuit. Hardware complexity of each circuit is investigated.