Abstract
This paper presents FEHSIM, a novel fault simulator which combines switch-level accuracy (i.e. switch-level fault models) with almost gate-level speed. FEHSIM uses a transistor netlist (e.g. SPICE) to first build the switch level model. In a second step, logic gates are extracted automatically, possibly leaving parts of the circuit such as pass transistors at the switch-level. Both models are kept during simulation. Faults are injected at the switch level. The key innovation in FEHSIM is a so called dynamic scheduler, which decides at run time if the simulation can be performed at gate-level without loosing accuracy. The results show a speed up factor of five compared with 'pure' switch level simulation maintaining full switch-level accuracy. >
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