Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter

Abstract

To overcome the von-Neumann bottleneck, static random-access memory (SRAM)-based in-memory computing (IMC) which enables parallel data processing in the memory, is being researched. To prevent the read disturbance issue, conventional 6T SRAM IMC employs Word-Line Under-Drive (WLUD), which leads to slow bit-line (BL) computing. Another approach to cope with the read disturbance is to use 10T SRAM cells in which BLs are decoupled for read and write operation. However, the overhead in the bit-cell array density is not affordable. In this paper, a fast 6T SRAM BL computing technique that prevents the read disturbance issue is proposed. The proposed technique adopts two consecutive short pulse WLs to avoid read disturbance, and skewed-inverter-based sense amplifiers to achieve the fast BL computation. A feedback loop for faster BL computing is also proposed. 128 × 128 IMC architecture is implemented using a 28nm CMOS process, and the delay of BL computing is improved 0.354X compared to WLUD in the worst case.