Abstract
The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
