FangTianSim: High-Level Cycle-Accurate Resistive Random-Access Memory-Based Multi-Core Spiking Neural Network Processor Simulator.

Hao Jiang,Lili Gao,Jinsong Wei,Ye Li,Jikai Lu,Qi Liu,Zhibin Wang,Yiqi Li,Xumeng Zhang,Junjie An,Tuo Shi

doi:10.3389/fnins.2021.806325

Abstract

Realization of spiking neural network (SNN) hardware with high energy efficiency and high integration may provide a promising solution to data processing challenges in future internet of things (IoT) and artificial intelligence (AI). Recently, design of multi-core reconfigurable SNN chip based on resistive random-access memory (RRAM) is drawing great attention, owing to the unique properties of RRAM, e.g., high integration density, low power consumption, and processing-in-memory (PIM). Therefore, RRAM-based SNN chip may have further improvements in integration and energy efficiency. The design of such a chip will face the following problems: significant delay in pulse transmission due to complex logic control and inter-core communication; high risk of digital, analog, and RRAM hybrid design; and non-ideal characteristics of analog circuit and RRAM. In order to effectively bridge the gap between device, circuit, algorithm, and architecture, this paper proposes a simulation model—FangTianSim, which covers analog neuron circuit, RRAM model and multi-core architecture and its accuracy is at the clock level. This model can be used to verify the functionalities, delay, and power consumption of SNN chip. This information cannot only be used to verify the rationality of the architecture but also guide the chip design. In order to map different network topologies on the chip, SNN representation format, interpreter, and instruction generator are designed. Finally, the function of FangTianSim is verified on liquid state machine (LSM), fully connected neural network (FCNN), and convolutional neural network (CNN).

Highlights

The success of artificial intelligence technology represented by deep neural network (DNN) today depends heavily on the development of big data and chip technology
FangTianSim can count the number of pulses, routing load, SRAM read–write frequency and RRAM read–write frequency
A more accurate RRAM model and analog neuron model can be introduced into FangTianSim to analyze the impact of more uncertainty of RRAM and analog circuit on spiking neural networks (SNNs)

Summary

Introduction

The success of artificial intelligence technology represented by deep neural network (DNN) today depends heavily on the development of big data and chip technology. In the early stage of SNN chip research, analog circuit was used to realize a neuron model (Silver et al, 2007) and cooperate with digital communication systems, such as networkon-chip (NoC) to realize the chip (Boahen, 2006; Schemmel et al, 2008; Qiao et al, 2015) This chip runs SNN with low power consumption, its function is very limited, and it is mostly used to study a small-scale brain model. People use advanced semiconductor technology and advanced asynchronous circuit design technology to realize large-scale integrated SNN chips These chips have high energy efficiency but can realize complex neuron models and a variety of synaptic plasticity. Good results have been obtained in the fields of handwritten character recognition, dynamic vision sensor (DVS) gesture recognition, and small sample gas classification (Akopyan et al, 2015; Davies et al, 2018; Deng et al, 2020)

Methods

Results

Conclusion