Failure Mechanisms in Passivated P+ -N Junctions Under Temperature and Bias Stress

Abstract

The mechanisms for anomalous increase of reverse current by reverse bias and temperature stress treatment on silicon p+-n planar junctions are analysed in detail. The effect of surface characteristics upon junction I-V curve is first surveyed generally by preparing the samples that have MOS type gate electrode in three types of configurations. Gate voltage to junction current curves are compared before and after the stress treatment and concluded that after the stress treatment, n-type inversion layers are formed on the very confined portions of the p-type diffused layer. It is also indicated that units having high resistivity n-type diffused layer. It is also indicated that units having high resistivity n-type substrate are easily deteriorated. From these facts, it is concluded that n-type inversion layers are formed only on the p-type surface where the acceptor densities decrease by the lateral diffusion under the oxide mask. As the mechanisms for anomalous increase of reverse current, the breakdown of field induced junctions by avalanching or tunneling is already proposed, however, in our case, tunneling mechanism is difficult to expect since n-type inversion layer is only formed on the lower acceptor portions of the diffused layers as stated above. This is experimentally verified from the large temperature coefficient of the reverse current and observation of no Esaki component in the forward current.