Failure Mechanism Study of GaAs Technology.

Abstract

Abstract : In this report we have discussed the characterization of the power FETs procured for this program and failure analysis of low noise devices, including wire bonding failures and environmental stress test failures. A method of etching gold while leaving the underlying refractory metals relatively unaffected was explained. An analysis of the Type A-6 low noise FET was given, in which a failure mode was discussed that involved possible channel doping compensation. Results were then presented on device failures from high and medium temperature stress tests on low noise FETs. A number of medium power devices were received from RADC for analysis. These were packaged FETs that had been subjected to various stresses at Texas Instruments on a RADC/TI reliability contract. Typically, the devices had failed during deliberate stressing to the maximum electrical limits or in temperature stress tests. Failure mechanism studies of two different ohmic contact metallizations showed that both fabrication procedures produced reliable contacts. Constant elevated temperature tests of gold-based gate diode FETs from two different manufacturers showed that one device type was considerably less prone to gate diode failure than the other, indicating the necessity of additional work on the gold gate versus aluminum gate reliability question. Failures were investigated that involve problems associated with gold contact pads overlaying aluminum gate pads with a refractory metal interface. Finally, temperature-accelerated studies of the resistance of aluminum gates were carried out. (Author)