Abstract
Power cycling tests on power modules consisting of insulated-gate bipolar transistors chips connected in parallel are reported. The following problems were found to degrade the properties of the modules: (1) Thick wire connections debonded after a low number of cycles because of mechanical strain. (2) Substrate assemblies deformed due to bimetallic effects, leading to poor thermal contact to the heatsink, and in some cases, to a cracking of electrical interconnects. (3) Soldering of substrates to large copper plates was of poor quality. The high number of large voids created intolerable differences in thermal resistance between the paralleled chips. It appears that the packaging technologies used are insufficient for power modules with paralleled chips when a high number of load cycles is expected.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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More From: IEEE Transactions on Components, Hybrids, and Manufacturing Technology
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