Facilitating Processor-Based DPR Systems for non-DPR Experts

Abstract

Currently, only Xilinx field programmable gate arrays (FPGAs) support dynamic partial reconfiguration (DPR). While there is currently some computer aided design (CAD) tool support for ISE-based DPR designs, none exists for microprocessor-based designs created in EDK. Creating DPR systems with the limited tool support currently available for ISE-based systems is already a challenging and complex process for novice DPR designers. These difficulties are severely compounded for potential microprocessor-based designs requiring a significant learning curve for novice DPR designers before they can successfully create their first working DPR system. This paper presents preliminary work towards extending the automation in Xilinx®'s current DPR design flow to include microprocessor based systems. The objective is to abstract low level details for novice designers, allowing them to focus on learning how to improve the quality of their design as opposed to how to perform the necessary manual transformations to generate a preliminary functional design. A case study demonstrated that the learning curve required to implement a first working design could be reduced by more than a factor of 15 times by improving the current automation available for microprocessor-based EDK designs.