Fabrication technology of void embedded silicon-on-insulator substrate

Abstract

Void embedded silicon-on-insulator (VESOI) substrate is a newly developed silicon-on-insulator (SOI) substrate for advanced complementary metal oxide semiconductor (CMOS) devices and integration technology. However, in the ion-cutting process for preparing the substrate, numerous hydrogen bubbles aggregate at the cut interface, which compresses the cavity structure and might cause the thin film above the cavity to be damaged and delaminated. Therefore, it is necessary to conduct in-depth research on the stress mechanism and process stability in the preparation of VESOI substrates. This study focuses on a single rectangular cavity structure and uses the fixed-supported beam theory to analyze its mechanical behavior during fabrication, and a three-dimensional model of cavity structure is constructed by using the finite element analysis tool. Through stress simulation, the failure mechanism of the cavity structure is identified, and the weak points are confirmed. The results show that the short side length (<i>w</i>), top silicon film thickness (<i>t</i>), and hydrogen bubble pressure are the main factors affecting the stress state of the top silicon film. When the <i>w</i>/<i>t</i> ratio exceeds 4–5, the silicon film will fracture owing to excessive tensile stress, and the fracture site is along the long side of the rectangular cavity. By increasing the thickness of the top silicon film slightly and adding support structures inside the cavity (to reduce <i>w</i>), this work successfully prepares high-quality 8-inch VESOI substrates that meet the requirements for the CMOS production line. The present study is expected to provide valuable idea for the development of integrated technologies relying on VESOI substrates.