Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

Yasunori Takeda,Daisuke Kumaki,Masashi Mamada,Takeo Shiba,Shizuo Tokito,Kenjiro Fukuda,Kazuma Hayasaka,Koji Yokosawa,Rei Shiwaku

doi:10.1038/srep25714

Abstract

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Highlights

Fabrication of OTFT-based circuits using conventional printing technologies is considered a promising approach due to advantages such as low capital investment, efficient utilization of material, and low production cost, motivating extensive research on the fabrication of organic CMOS integrated circuits either entirely or in part by using printing methods
In an organic transistor with printed electrodes, surface treatment of the source and drain electrodes using a self-assembled monolayer (SAM) layer is very important for improving the OTFT characteristics[22]
The electrode surface treatment for both OTFT device types can be carried out using a simple immersion process

Summary

Introduction

Fabrication of OTFT-based circuits using conventional printing technologies is considered a promising approach due to advantages such as low capital investment, efficient utilization of material, and low production cost, motivating extensive research on the fabrication of organic CMOS integrated circuits either entirely or in part by using printing methods. The optimization of the electrical characteristics of p-type and n-type OTFT devices requires the modification of the electrode surfaces by using a self-assembled monolayer (SAM)[15], oxide layer[16], or polymer layer[17] processes for the different semiconductor materials Complex processes such as SAM patterning using a plasma treatment[5] are required to form the source and drain electrodes of each of n and p type OTFT devices on the same substrate, which are unsuitable for volume production and prevent the use of organic transistors in practical applications. To reduce the complexity of the CMOS inverter circuit fabrication, we developed a sophisticated stacked-structure printing process This fabrication process exhibits the following advantages: 1) simple electrode surface modification with different SAM layers, 2) use of a common gate electrode layer to simplify the circuit layout, 3) top-gate, bottom-contact (TG-BC) device structure to maximize and take advantage of the performance of the n-type OTFT. We successfully fabricated these integrated circuits on a 1-μ m thick film substrate and have demonstrated their ability to operate even when this film is compressed

Methods

Results

Conclusion