Fabrication of SOI wafers with buried cavities using silicon fusion bonding and electrochemical etchback

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This paper describes a new technique for batch fabrication of silicon-on-insulator (SOI) wafers for microelectromechanical systems (MEMS) applications by silicon wafer bonding techniques. The process permits the inclusion of buried cavities in the SOI wafers, providing a useful tool for sensor and actuator fabrication using the resulting wafers. A low-cost electrochemical etchback step is used to define accurately the thickness of the remaining single-crystal material even though the two wafers are bonded with an intermediate insulating oxide layer. The results presented include guidelines for backside contact definition which maximize the useful silicon area as a function of doping level. The final single-crystal silicon thickness is uniform to within 0.05 μm (standard deviation) and does not require any costly high-accuracy polishing steps.