Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging

Abstract

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.