Fabrication of novel self-aligned metal insulator semiconductor field effect transistors (MISFETs) on InP by a S interface engineering technique

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In this paper we demonstrate for the first time that self-aligned metal insulator semiconductor field effect transistors (MISFETs) can be realized on InP by incorporating an effective surface passivation technique in the fabrication process. A chemical sulfur treatment is used to passivate the InP – indirect plasma silicon nitride interface that results in interface state densities (Dit) in the low 1011/cm2 eV. It is observed that while passivated self-aligned MISFETs subjected to post-passivation high-temperature process cycles up to 700 °C exhibit acceptable transistor characteristics, unpassivated MISFETs using the same process do not show any transistor action. The passivation procedure has been successfully used to demonstrate for the first time a self-aligned InP–InGaAs–InP heterojunction insulated gate FET. We conclude from this work that interface engineering techniques like the one used in this study would be essential to realize and (or) improve the performance of self-aligned FET structures based on InP. The fabrication process described here can be directly applied to similar interface engineering techniques.