Abstract

n-Channel metal–oxide–semiconductor field-effect transistors with gate lengths ranging from 10–0.2 μm were fabricated for the first time on device quality 300–500 Å ultrathin silicon on sapphire (SOS) wafers using electron-beam exposure for the gate level patterning step. Working devices were found over a large area on a group of six 4 in. wafers, including two wafers with approximately 1000 Å thick silicon films used for comparison, each with slightly different fabrication conditions. An arsenic implant was used to dope the source–drain regions of the devices. Threshold voltages were measured across each wafer for a variety of gate lengths, from which both an average value and spread was obtained. Both the average value and spread were seen to correlate with the silicon film thickness and thickness variations measured directly. Similar measurements were obtained for subthreshold slopes. Extrinsic transconductance was measured to be as high as 42 mS/mm for the smaller devices, heavily reduced due to source and contact resistance from the doped thin silicon (at about 250 Ω/square for the 500 Å films) leading up to the channel. Some of the special difficulties of electron-beam patterning on thin-film SOS are addressed.

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