Abstract
The fabrication of a lateral single electron memory (LSEM) based on the integration of a metallic multiple tunnel junction (MTJ) and a memory node (MN) on a Si metal oxide semiconductor field effect transistor (MOS) has been investigated. High resolution electron beam lithography (HREBL) was used to fabricate devices presenting good morphological characteristics. The MN can be made as narrow as 50 nm, with an MTJ comprising a 5×5 array of sub-5 nm Au islands deposited by thermal evaporation, and implemented on a short 0.5 μm channel MOS. An operating temperature close to 77 K with the two memory levels relying on the excess or shortfall of approximately 30 electrons is expected.
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