Fabrication of 6 nm gap on silicon substrate for power-saving appliances

Abstract

We document a thermal oxidation process for the reproducible fabrication of 6-nm gaps on silicon-on-insulator (SOI) substrate. Nanogaps sizes of this dimension are implicated to eliminate contributions from double-layer capacitance in the dielectric sensing of proteins or nucleic acids. The method combines conventional photolithography and pattern-size reduction technique to create a desired-size gap. The gaps are physically characterized with a field emission scanning electron microscopy (FESEM). Preliminary results show that gap-size reduction provides an improvement in conductivity, permittivity and capacitance parameters, reflecting the potential applications of the fabricated structures in low-power consuming electrical devices. The task is completed with two chrome masks: the first mask is for the nanogap pattern and the second one is for the electrodes. An improved resolution of pattern size is obtained by controlling the oxidation time of the final cycle. The reproducibility of the method is proven in triplicate experiments. We believe the method can be used in the industrial production of desired-size nanogaps on a variety of low-cost substrates. Key words: Nanogap, sequential oxidation, wet etching, double-layer capacitance, dielectric sensing, biomolecules.