5 nm gap via conventional photolithography and pattern-size reduction technique

Abstract

A simple method for the fabrication of nanogaps of less than 6 nm by conventional photolithography combined with patterned-size reduction technique is presented. The method is based on the complete conversion of a photolithographically embedded polysilicon structure on a silicon wafer into a semiconductor oxide layer and subsequent stripping of the oxide layer by etching with a buffer oxide etching (BOE) solution. With this technique, there are no principal limitations to fabricate nanostructures with different layouts and dimensions along with an improved pattern size resolution. The method is demonstrated by preparing self-aligned nanogaps of 5–6 nm dimensions on a Si–SiO2substrate. Polysilicon material is used to fabricate the nanogap structure and gold is used for the electrodes. Two chrome masks are used to complete this work. The first one is for the nanogap pattern and the second one is for the pad electrode. The fabricated structure is optically and electrically characterized with a field emission scanning electron microscope (FESEM) and dielectric analyzer (DA). Key words: Nanogap, photolithography, pattern-size reduction, wet etching, optical and electrical characterization.