Fabrication of 22 nm T-gates for HEMT applications

Abstract

This paper reports a new method for the fabrication of sub-25nm T-gates for high electron mobility transistors (HEMTs). For robust fabrication, it may be advantageous to employ a two-step process where the gate foot and head can be separately defined. The new process uses ZEP520A electron beam resist as a mask for SF6-based anisotropic reactive ion etching of ICP-deposited silicon nitride to define the gate foot. The gate head structure, defined in PMMA/LOR/UVIII, is then lithographically aligned to the gate foot. All electron beam lithography was performed using a Vistec VB6 UHR EWF tool. The design flexibility, mechanical stability, gate resistance and plasma-induced damage of this new method and its suitability for integration in a HEMT process flow are evaluated in this paper. This work has led to the high-yield fabrication of robust 22nm T-gates.