Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors

Abstract

Fifty nanometre gate length T-gates In 0.52A1 0.48As/In 0.53Ga 0.47As high electron mobility transistors (HEMTs) on a InP substrate were fabricated with high resolution electron-beam (e-beam) lithography using a novel UVIII/LOR/PMMA T-gate resist stack and with a non-selective digital wet etch gate recess technology. The reproducibility of the gate lithography depends on the substrate slope when mounted on the holder of e-beam lithography tool. This mounting effect is almost eliminated by calibrating the tool using a specially fabricated marker on the wafer instead of the holder marker as in usual. Initial devices exhibited a maximum transconductance ( g m) of 950 mS/mm and a current cut-off frequency ( f t) of 300 GHz.