Abstract
In this work, Metal Insulator Semiconductor (MIS) device is fabricated by depositing Graphene Oxide (GO) layer between the top and bottom Polyvinyl Alcohol (PVA) layers to act as an insulating layer. Topographical study of Ag/PVA/GO/PVA/n-Si/Ag device is done by Field Emission-Scanning Electron Microscopy (FE-SEM) technique. The image clearly showed the multilayered sandwiched structure having GO embedded between PVA layers. The comparative study of the effect of interface trap states, series resistance (Rs) and an insulating layer on the different layers of device performance is done using capacitance-conductance characteristics. The presence of peaks in capacitance-conductance curves revealed the presence of interface trap states in the fabricated device. The C–V measurements were taken in the frequency range of 5 kHz to 1 MHz. The interfacial state density (Nss) is found to be of the order of 1011 cm−2 eV−1 which is calculated using Hill-Coleman's method. The increase in leakage current through residual native oxide is verified by calculating the series resistance. The deviation from the ideal behavior of capacitance and conductance characteristics is observed which is attributed to Nss and Rs. The device fabricated unfolded the existence of the capacitance roll-off phenomenon.
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