Abstract

Design space exploration and sensitivity analysis for electrical performance of high-speed serial links is a critical and challenging task for a robust, cost-efficient, and signal-integrity-compliant channel design. The generation of time-domain (TD) metrics like eye height and eye width at higher bit error rates requires longer bit sequences in TD circuit simulation, which is compute time intensive. Intelligent techniques to identify smaller design sets that cover the design space optimally may provide incorrect sensitivity analysis. This paper explores learning-based modeling techniques that rapidly map relevant frequency-domain metrics like differential insertion loss and total cross talk, in the presence of equalization, to TD metrics like eye height and eye width, thus facilitating a full-factorial design space sweep. Numerical results performed with multilayer-perceptron-based artificial neural network as well as least-squares support vector machine (LS-SVM) on Serial ATA 3.0 and Peripheral Component Interconnect Express Gen3 channels generate an average error of less than 2%.

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