Abstract

Validation of high-speed interface performance in a given design space from a Signal Integrity (SI) perspective requires Bit Error Rate (BER) computation. Eye Height (EH) and Eye Width (EW) are used to determine the quality of an interface for a given set of design parameters and frequency of operation. EH, EW and BER estimation requires Time Domain (TD) simulation of complex channel models over billions of bits, which is a time, compute power and memory intensive process. Statistical and optimization techniques such as Design of Experiments (DoE) based on generation of design sets that span the design space optimally exist today. However, it has been shown that DoE based simulations might result in in-accurate sensitivity analysis for highly nonlinear design spaces. Also, the size of a DoE set scales exponentially with the number of design variables. It has been shown in [5] that TD metrics EH and EW, in absence of cross-talk, can be mapped from FD metrics like Return Loss (RL) and Insertion Loss (IL) using Artificial Neural Networks (ANN). The training of the ANNs requires DoE for the existing method. In this paper, an alternative technique to DoE, for generating a training set for ANN is presented, which remains constant over several number of design variables, and scales only in the number of FD metrics used to map to TD metrics and the number of samples in FD. Simulations for SATA 3.0 channel topology with and without cross-talk in TD are presented to quantify the accuracy of the said approach.

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