Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Abstract

Trap densities ( D t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance–voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D t is very roughly 10 18 cm −3 eV −1 near the midgap and becomes tail states near the conduction and valence bands. As a result, D t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing.