Extraction of the Top and Sidewall Mobility in FinFETs and the Impact of Fin-Patterning Processes and Gate Dielectrics on Mobility

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, we propose a simple methodology for the extraction of the top and sidewall mobility in FinFET like triple-gate device architectures. The underlying assumptions are outlined and verified by simulations and experiments. Using this model, the top and sidewall mobility on both n- and p-channel FinFETs, fabricated with various fin-patterning processes and gate dielectrics, was extracted. It is shown that the choice of the hard mask and corner-rounding processes and the gate dielectric impacts the top and sidewall mobility differently. The proposed methodology provides a powerful tool for technologists to optimize the gate stack and fin-patterning processes. It also provides a simple model to capture the anisotropy of mobility in device and circuit simulators. </para>