Extension of patterning technologies down to sub-10nm half pitch

Abstract

Patterning methods for sub-10nm half pitch are discussed. Four patterning methods are selected due to discussing their feasibility: immersion lithography with self-aligned octuplet patterning (Imm-SAOP), EUVL with self-aligned double patterning (EUV-SADP), EUVL with litho-etch-litho-etch (EUV-LELE) and EUVL with directed self-assembly (EUV-DSA). There are two significant issues in lithography process and etch process: iso-dense bias and CD variation. Relaxation of design rule except for memory cell makes iso-dense bias issue not critical. However, CD variation influences directly device characterization. CD variation formula are established for the four patterning method described above. Assuming the challenging spec for each unit process, CD variation is estimated for the four patterning methods using the formula. Although EUV-SADP and EUV-DSA are candidates for sub-10nm patterning technology, Imm-SAOP and EUV-LELE are out of spec required from device characteristics.