Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm

Abstract

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks. A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.