Abstract
Synchronization is a critical operation in digital communications. An important part of the synchronizer structures relies on the digital phase locked loop (PLL) principle. The PLL structure can be derived from the maximum likelihood (ML) criterion, leading to a sinusoidal phase error detector (PED). This PED offers robustness at low signal-to-noise ratio (SNR) transmissions. However, the reduced linear zone of the PED characteristic leads to unwanted cycle slips in the presence of large frequency offset. On the other side, the tanlock PED has an extended linear characteristic but is still limited in the case of simultaneous large frequency offset and low SNR transmissions in both acquisition and tracking modes. We propose in this paper a software PLL which stays quasi- linear for low SNR and large frequency offset transmissions. Simulations show that the proposed system is robust to cycle slips. Moreover, this system can be designed with the classical tools used for the linear model of the PLL.
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