Extended Instruction Set Design for Transcoding Application Using RISC-V ISA

Abstract

RISC-V is a coeval, refined and flexible open-source instruction set architecture (ISA) basically designed for computer architecture research. It presents a conventional and open base ISA and competitive reference hardware designs that anybody can freely use as a base for further innovation. This makes RISC-V unambiguously suitable for the later phase of development in microprocessor hardware architectures. Transcoding plays a crucial role in a multimedia streaming service. Content owners and publishers require transcoders to modify their data to different bitrates, formats and qualities before streaming them to end users with the best quality of service. In this paper, improving the performance of transcoding application using RISC–V ISA is explained by adding an instruction to RISC-V instruction set architecture. The three stages of a pipeline architecture, i.e., fetch, decode, and execute are verified. Each stage except multiplication operations taking one clock cycle used in DCT operation and the designed system is synthesized using Spartan 6 XC6SLX45 fgg484 device.KeywordsTranscodingInstruction set architecture (ISA)BitrateMultimedia streamingRISC-V