Detection of atrial fibrillation with an optimized neural network on a RISC-V-based microcontroller for efficient integration into ECG patches

Abstract

Atrial Fibrillation (AF) is one of the most common heart arrhythmias. It is known to cause up to 15 % of all strokes. In current times, modern detection systems for arrhytmias, such as single-use patch electrocardiogram (ECG) devices, have to be energy efficient, small and affordable. In this work, an artificial neural network (NN) for the detection of AF is optimized to assess the minimum requirements in memory and frequency for inference on the AIRISC, a microcontroller based on the RISC-V instruction set architecture (ISA). The AIRISC will be synthesized as a System-On-Chip (SoC) solution later in the project. Hence, a 32-bit floating-point-based NN was analyzed. To reduce the silicon area needed, the NN was quantized to 8-bit fixed-point integer datatype, as the floating-point unit (FPU) is one of the largest modules in silicon area needed for the SoC. To compensate the losses of quantization, the network is expanded and optimized for run-time and memory requirements. The resulting NN has a 7.5 % lower run-time in clock cycles and 2.2 p.p. lower accuracy as the f1oating-point-based net, while requiring 65 % less memory and no FPU within the hardware. The presented approach can achieve one inference per second at a clock frequency of 62 kHz.