Extendable generic base verification architecture for flash memory controllers based on UVM

Abstract

This paper introduces an extendable and generic base architecture built on Universal Verification Methodology (UVM) for verifying Flash memory controller designs. The base architecture aims to create a generic and configurable abstraction verification environment for Flash memory controller designs. It integrates the essential UVM Verification Components (VCs), defines the functionalities of the VCs, and connects them in a generic and dynamic approach. It also implements some base functions and tasks for Flash memory controller verification environment. In addition, it provides the implementation of the UVM phases' functions and tasks. The configuration mechanism of the base architecture supports the verification of multiple memory controllers and other peripherals. This paper guides the verifier where and how to put the behavior of Flash memory controller in its correct and suitable place in the base architecture to serve the idea of reusability which the UVM originally is built on. This paper introduces a case study of the base verification architecture and provides its experimental result. This paper also introduces a lot of UVM knowledge to make the verifier efficiently exploit this base architecture and reuse it in many other verification projects.