Abstract
This paper presents an analysis on the efficiency of dataflow SIHFT techniques applied to out-of-order superscalar processors. A set of five SIHFT techniques are applied to a benchmark of applications running in different configurations of the complex BOOM superscalar processor. A fault injection campaign is performed by simulating over 42 million faults affecting all system's flip-flops, and the efficiency of each technique is tested regarding IPC gain, sensitivity reduction, and execution time. Results are presented individually for each micro-architectural structure, showing improvements in sensitivity reduction and IPC gain, but a deterioration in execution time. Conclusions may lead designers to develop less sensitive complex processor architectures.
Published Version
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