Exploring the Engineering of Copper Grains to Electroplate Bamboo-Like Structures and Foster Cu (111) Oriented Films in Pursuit of Enhanced Device Reliability

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In semiconductor manufacturing, precisely controlling copper (Cu) grain size and orientation within vias is pivotal for ensuring integrated circuit reliability. This paper extensively explores the adaptable characteristics inherent to the bamboo process when applied to Cu (111) grain-size engineering. The study underscores the complete mastery of grain size and orientation within vias, offering an indispensable tool for advancing next-generation copper electroplating methodologies. Utilizing X-ray diffraction (XRD) analysis, a distinctive Cu (111) preferential orientation is unveiled up to 88%. Furthermore, Focused ion beam (FIB)/scanning electron microscopy (SEM) images show a film free of voids, defects, and conspicuous anomalies such as waist curves, delamination, or film cracking, even after annealing at temperatures up to 250°C. The bamboo process is achieving notably low impurity levels across a substantial range of current densities, spanning from 2 to 6 ASD with a total impurities range of 3-5 ppm. Significantly, the process allows for meticulous control over grain size, enabling the generation of fine and large copper grains tailored to specific application requirements. The bamboo suppressor incorporated into the process demonstrates remarkable bottom-up capabilities, promising further exploration of its interaction with additional additives. These novel additives are synthesized in house to achieve these functional performance and more. Design of experiment (DOE) reveals that a low leveler concentration can achieve the desired bamboo grain structure within the vias. Additionally, accelerator concentration directly impacts grain size, reducing it with higher concentrations, while reduced process agitation increases grain size. The study investigates waveform-based plating processes, each unveiling distinctive grain size characteristics. Remarkably, a two-step waveform (one-bath) approach yields larger grain sizes than a one-step plating process. Moreover, this study delves into the intricate nuances of controlling copper (Cu) grain size within vias through the versatile bamboo process, with particular attention to the influence of current density. At a low current density of 2 ASD, the process produces an ultra-fine grain copper film. Transitioning to a moderate current density of 3 ASD results in a deposited film with a dynamic mixture of fine and large grains. At a high current density of 6 ASD, large bamboo-like copper grains form. FIB of films plated at 2 and 3 ASD and annealed at 125 °C reveal substantial grain growth. In addition, films deposited at 6 ASD exhibit larger grains than at 2 ASD, yet we observe further grain growth upon annealing at 200 °C. Further annealing at 250 °C for 2 hours induces an impressive 71% increase in grain size. This comprehensive study provides invaluable insights into the precise manipulation of copper grain size and orientation using the bamboo process, holding significant promise for enhancing the reliability of integrated circuits in semiconductor manufacturing.