Abstract
RapidIO ( http://rapidio.org/ ) technology is a packet-switched high-performance fabric, which has been under active development since 1997. The technology is used in all 4G/LTE base stations worldwide. RapidIO is also used in embedded systems that require high reliability, low latency, and deterministic operations in a heterogeneous environment. RapidIO has several offloading features in hardware, therefore relieving the CPUs from time- and power-consuming work. Most importantly, it allows for remote direct memory access and thus zero-copy data transfer. In addition, it lends itself readily to integration with field-programmable gate arrays. In this paper, we investigate RapidIO as a technology for high-speed data acquisition (DAQ) networks, in particular the DAQ system of an LHC experiment. We present measurements using a generic multiprotocol event-building emulation tool that was developed for the LHCb experiment. Event building using a local area network, such as the one foreseen for the future LHCb DAQ, puts heavy requirements on the underlying network as all data sources from the collider will want to send to the same destinations at the same time. This may lead to an instantaneous overcommitment of the output buffers of the switches. We will present results from implementing an event building cluster based on RapidIO interconnect, focusing on the bandwidth capabilities of the technology as well as its scalability.
Highlights
R APIDIO [1] is a high-performance, low pin count, packet-switched system-level interconnect standard
Notable logical operations introduced in the protocol specification include read/write operations and messaging [channelized messaging (CM)]
Channelized messages were used for commands, which are utilized by all unit types to organize the event building. rDMA buffers were used as data aggregation buffers
Summary
R APIDIO [1] is a high-performance, low pin count, packet-switched system-level interconnect standard. It is mainly utilized within embedded systems in chip-to-chip and board-to-board communications, but on account of a number of appealing features, such as low latency combined with scalability, it lends itself well in other contexts, such as a larger scale fabric in high-performance computing (Fig. 1). RapidIO is primarily hardware implemented, offering error handling at the physical level as well as hardware termination This enables low latencies and offloads the CPU, permitting the scale-up of a realtime system. Our particular project aims to explore RapidIO in different domains of networking applications. For this purpose, ROOT [3] and data acquisition protocol-independent performance evaluator (DAQPIPE) [4] were selected as suitable candidates.
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