Abstract
Emerging memories have been developed to achieve energy efficiency target in the Internet of Things era. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile (NV) memory has demonstrated attractive performance because of zero standby power, reduced switching power, infinite endurance, and high density. Meanwhile, hybrid STT-MTJ/CMOS integration is a promising solution to overcome the bottleneck of dynamic and leakage power dissipation. In this paper, ultralow power methodologies are developed at device and circuit level in 28 nm fully depleted silicon on insulator CMOS technology. Supply voltage scaling, near-/sub-threshold (V t ) operation, and back-bias adjustment are demonstrated, showing 81% dynamic power reduction under 0.6 V near-V t sensing operation, with the tradeoff of 6.2% increased sensing error rate. Through the case study on STT-MTJ-based NV flip-flops (NV-FFs), up to 76% dynamic and 79% leakage power saving can be realized in ultra-low power NV-FF implementation.
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