Exploring Absolute Differences Arithmetic Operators for Power and Area-Efficient SAD Hardware Architectures

Abstract

Managing the energy requirements of video encoders has been an important research topic throughout the latest years, given the limited resources of battery-powered systems. Sum of Absolute Differences (SAD) stands out among the most costly steps in the video encoding process compliant with the High Efficiency Video Coding (HEVC) standard. This metric is mainly used to explore temporal redundancies during the inter prediction stage of the encoder, and it is applied by adding the absolute differences of the colocalized pixels of two video blocks, as a means of measuring the similarity between them. SAD architectures are usually designed by using an adder tree, with its first level consisting of subtractors and absolute operators. This paper explores various structures of absolute operators in the context of SAD architectures, in order to define the most suitable implementation for a power-efficient SAD module. Besides the analysis of several different models, we exploit the use of pipelining, and the impact of varying block input bitwidth, to determine which versions scale better with the increase of input size. We have synthesized the architectures for ASIC CMOS technology using real-input vectors taking the delays into consideration, with an ST 65 nm standard cells library, and compared them with the default absolute operator macrofunction from the synthesis tool.