Low power sum of absolute differences architecture using novel hybrid adder

Abstract

Sum of Absolute Differences (SAD) is an intensive time-consuming operation of state-of-art video encoders. It is used as a block matching metric inside Motion Estimation (ME) and also on mode decision in Intra Prediction. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. Due to the simplicity, the SAD metric is the better choice when the video encoders project space is focused on power efficiency. In order to reduce the SAD power dissipation, this work proposes a new hybrid encoded adder operator. The power-efficient hybrid encoding representation groups m bits and uses gray encoding to potentially reduce the switching activity, both internally and the inputs of the arithmetic operators. The SAD architecture, using the proposed hybrid adder operator, was synthesized to 45 nm standard cell technology and compared in terms of power dissipation using real video sequences. Results show that 7.58% of total power is saved (on average) when compared with SAD architecture using the macro-function adder from the synthesis tool. Compared to SAD architecture using state-of-the-art hybrid adder, our architecture saves 12.97% on average power dissipation.