Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip

Ing-Jer Huang Ing-Jer Huang,Chung-Fu Kao Chung-Fu Kao

doi:10.1109/apasic.2000.896970

Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip

Ing-Jer Huang Ing-Jer Huang, Chung-Fu Kao Chung-Fu Kao

https://doi.org/10.1109/apasic.2000.896970

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Publication Date: Aug 28, 2000

Citations: 2

Affiliation: National Sun Yat-sen University

#System-on-Chip Chip #Hierarchical Styles + Show 8 more

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Abstract

This paper explores architectural alternatives in the integration of embedded in-circuit emulation into a SoC (System-on-Chip) chip with multiple microprocessor (microcontroller) cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.

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