A Progressive Automatic Logic Synthesis Method for Timing-Limited SoC Design

Abstract

With the continuous progress of semiconductor technology, integrated circuits (ICs) have been applied to various electronic devices, such as computers, mobile phones, industrial controllers and so on. System on chip (SoC) is a special IC chip with system architecture, generally including computing logic, acceleration logic, and peripheral units. It has the advantages of small size, low power consumption, and high flexibility, and has been widely used. In the SoC chip design process, logical timing is usually very tight, which will lead to great difficulties in the logic synthesis stage. In general, the conventional synthesis method will manually increase the proportion of path groups, low voltage threshold (LVT) cells, ultra-low voltage threshold (ULVT) cells to improve timing performance, but its timing closure is slow, which will prolong the whole SoC chip design cycle. In order to improve the convergence speed of the SoC chip logic synthesis, this paper proposes a progressive automatic logic synthesis (PALS) method, which adopts progressive form to add path groups, insert LVT and ULVT cells, and performs iteration automatically. In this method, the iterative optimization constraints have the advantages of gradual progression and comprehensive coverage, which improves the convergence speed of logic synthesis effectively. In addition, ARM CortexA7 is synthesized using PALS method, and the experimental results show that the timing convergence time of the PALS method proposed in this paper is reduced by 12% compared with the conventional method, proving the superiority of the PALS method.